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A82DL16X4T(u) series stacked multi-chip package (mcp ) flash memory and sram, A82DL16X4T(u) 16 mega bit (2mx8 bit/1mx16 bit) cmos 3.3 volt-only, simultaneous operation flash memory and 4m (256kx16 bit) static ram preliminary preliminary (august, 2005, version 0.0) amic technology, corp. document title stacked multi-chip package (mcp) flash memo ry and sram, A82DL16X4T(u) 16 megabit (2mx8 bit/1mx16 bit) cmos 3.3 volt-only, simultaneous operation flash memory and 4m (256kx16 bit) static ram revision history rev. no. history issue date remark 0.0 initial issue august 15, 2005 preliminary
A82DL16X4T(u) series stacked multi-chip package (mcp ) flash memory and sram, A82DL16X4T(u) 16 mega bit (2mx8 bit/1mx16 bit) cmos 3.3 volt-only, simultaneous operation flash memory and 4m (256kx16 bit) static ram preliminary preliminary (july, 2005, version 0.0) 1 amic technology, corp. distinctive characteristics mcp features single power supply operation 2.7 to 3.6 volt high performance - access time as fast as 70ns package 69-ball tfbga (8x11x1.4 mm) industrial operating temperature range: -40 c to 85 c for ?u; -25 c to 85 c for ?i flash features architectural advantages simultaneous read/write operations - data can be continuously read from one bank while executing erase/program f unctions in other bank - zero latency between read and write operations multiple bank architectures - three devices available with different bank sizes (refer to table 2) package - 69-ball tfbga (8x11x1.4 mm) top or bottom boot block manufactured on 0.18 m process technology - compatible with am42dl16x4d devices compatible with jedec standards - pinout and software compatible with single-power-supply flash standard performance characteristics high performance - access time as fast as 70ns - program time: 7s/word typical utilizing accelerate function ultra low power consumption (typical values) - 2ma active read current at 1mhz - 10ma active read current at 5mhz - 200na in standby or automatic sleep mode minimum 1 million write cycles guaranteed per sector 20 year data retention at 125c - reliable operation for t he life of the system software features supports common flash memory interface (cfi) erase suspend/erase resume - suspends erase operations to allow programming in same bank data polling and toggle bit - provides a software method of detecting the status of program or erase cycles unlock bypass program command - reduces overall programming time when issuing multiple program command sequences hardware features any combination of sectors can be erased ready/ busy output (ry/ by ) - hardware method for detecting program or erase cycle completion hardware reset pin ( reset ) - hardware method of resetting the internal state machine to reading array data wp /acc input pin - write protect ( wp ) function allows protection of two outermost boot sectors, r egardless of sector protect status - acceleration (acc) functi on accelerates program timing sector protection - hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector - temporary sector unprotect allows changing data in protected sectors in-system lp sram features power supply range: 2.7v to 3.6v access times: 70 ns (max.) current: very low power version: operating: 35ma(max.) standby: 10ua (max.) full static operation, no clock or refreshing required all inputs and outputs are directly ttl-compatible common i/o using three-state output output enable and two chips enable inputs for easy application data retention voltage: 2.0v (min.)
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 2 amic technology, corp. general description the a82dl16x2t(u) family consists of 16 megabit, 3.0 volt- only flash memory devices, organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. word mode data appears on i/o 0 ?i/o 15 ; byte mode data appears on i/o 0 ? i/o 7 . the device is designed to be programmed in-system with the standard 3.0 volt vcc supply, and can also be programmed in standard eprom programmers. the device is available with an access time of 70ns. the devices are offered in 69- ball fine-pitch bga. standard control pins?chip enable ( ce_f ), write enable ( we ), and output enable ( oe )?control normal read and write operations, and avoid bus contention issues. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provid ed for the program and erase operations. simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into two banks. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the A82DL16X4T(u) devices uses multiple bank archi- tectures to provide flexibility for different applications. three devices are available with these bank sizes: device bank 1 bank 2 dl1624 2 mb 14 mb dl1634 4 mb 12 mb dl1644 8 mb 8 mb A82DL16X4T(u) features the device offers complete compatibility with the jedec single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to readin g from other flash or eprom devices. the host system can detect w hether a program or erase operation is complete by using the device status bits: ry/ by pin, i/o 7 ( data polling) and i/o 6 /i/o 2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. t he device is fully erased when shipped from the factory. hardware data protection measures include a low vcc detector that automatically i nhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. this can be achieved in-s y s t e m or via programming equipment. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 3 amic technology, corp. pin configurations 69-ball tfbga top view a5 a6 a10 b3 b4 b5 b6 b7 b8 c3 c4 c5 c6 c7 c8 c9 d4 d4 d5 d6 d7 d8 d9 e3 e4 e7 e8 e9 e10 f3 f4 f7 f8 f9 f10 nc nc nc a7 lb_s wp/acc we a8 a11 a6 ub_s reset ce2_s a19 a12 a15 a5 a18 ry/by nc a9 a13 nc a4 a17 a10 a14 nc nc vss i/o1 i/o6 nc a16 nc flash only sram only shared a1 b1 c2 d2 e1 e2 f1 f2 nc nc a3 a2 nc a1 nc a0 g3 g4 g5 g6 g7 g8 g9 h3 h4 h5 h6 h7 h8 h9 i/o9 i/o3 i/o4 i/o13 i/o15(a-1) byte_f i/o0 i/o10 vcc_f vcc_s i/o12 i/o7 vss g2 h2 ce_f oe ce1_s j3 j4 j5 j6 j7 j8 k5 k6 k10 i/o8 i/o2 i/o11 nc i/o5 i/o14 nc nc nc k1 nc special handling instructions for tfbga package special handling is required for flash memory products in tfbga packages. flash memory devices in tfbga packages may be damaged if ex posed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if the package body is expose d to temperatures above 150c for prolonged periods of time
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 4 amic technology, corp. product information guide part number A82DL16X4T(u) speed options standard voltage range: vcc_f/vcc_s=2.7-3.6v 70 max access time (ns) 70 ce_f / ce_s access (ns) 70 oe access (ns) 40 mcp block diagram 16m bit flash m emory 4m bit static ram vcc_s vss vcc_f vss a19 to a0 ry/by i/o 15 (a-1) to i/o 0 i/o 15 (a-1) to i/o 0 i/o 15 (a-1) to i/o 0 a17 to a0 a19 to a0 byte_f wp/acc ce_f ce1_s ce2_s reset ub_s lb_s o e we
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 5 amic technology, corp. flash block diagram a0-a19 a0-a19 a0-a19 state control & command register i/o 0 -i/o 15 a0-a19 a0-a19 reset we ce_f wp/acc ry/by status control byte_f oe byte_f upper bank address lower bank address i/o 0 -i/o 15 upper bank x-decoder y-decoder latches and control logic upper bank x-decoder y-decoder latches and control logic i/o 0 -i/o 15 i/o 0 -i/o 15 vcc_f vss oe byte_f
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 6 amic technology, corp. pin descriptions pin no. description a0 - a19 address inputs i/o 0 - i/o 14 data inputs/outputs i/o 15 data input/output, word mode i/o 15 (a-1) a-1 lsb address input, byte mode ce_f chip enable ce_s chip enable (sram) we write enable oe output enable wp /acc hardware write protect/acceleration pin reset hardware reset pin, active low byte_f selects 8-bit or 16-bit mode ry/ by ready/ busy output vss ground vcc_f power supply (flash) vcc_s power supply (sram) nc pin not connected internally logic symbol a0-a19 ce_f oe we reset byte_f ry/by i/o 0 -i/o 15 (a-1) 20 16 or 8 wp/acc ce_s
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 7 amic technology, corp. sram block diagram decoder 512 x 8192 memory array column i/o input data circuit control circuit vcc_s vss i/o0 a17 a16 a0 we input data circuit i/o8 i/o15 oe i/o7 ce1_s ce2_s ub_s lb_s
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 8 amic technology, corp. device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that st ore the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the st ate machine outputs dictate the function of the device. the appr opriate device bus operations table lists the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. table 1-1. device bus operations ? flash byte mode ( byte_f = v ih ) operation (notes 1, 2) ce_f e1_s c ce2_s oe we a0- a19 lb_s (note3) ub_s (note3) reset wp /acc (note 4) i/o 7 ? i/o 0 i/o 15 ? i/o 0 h x read from flash l x l l h a in x x h l/h i out i out h x write to flash l x l h l a in x x h (note 4) i in i in h x standby vcc 0.3 v x l x x x x x vcc 0.3 v h high-z high-z l x output disable l l h h h x x l h l/h high-z high-z h x x l flash hardware reset x h x x x x x x l l/h high-z high-z x l sector protect (notes) l h x h l sa, a6 = l, a1 = h, a0 = l x x v id l/h i in x sector unprotect (note 5) l x l h l sa, a6 = h, a1 = h, a0 = l x x v id (note 6) i in x h x i in high-z temporary sector unprotect x x l x x a in x x v id (note 6) i out i out h l high-z i out l h i out high-z read from sram h l h l h a in l l h x i in i in h l high-z i in write to sram h l h x l a in l h h x i in high-z legend: l = logic low = v il , h = logic high = v ih , v id = 8.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sector address, a in = address in, i in = data in, i out = data out notes: 1.other operations except for those indi cated in this column are inhibited. 2.do not apply ce_f = v il , ce1_s = v il and ce2_s = v ih at the same time. 3.don?t care or open lb_s or ub_s . 4.the sector protect and sect or unprotect functions may also be implem ented via programming equipment. see the ?sector/sector block protecti on and unprotection? section. 5. if wp /acc = v il , the two outermost boot sect ors remain protected. if wp /acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotect ed using the method described in ?sector/sector block protection and unprotection?. if wp /acc = v hh , all sectors will be unprotected.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 9 amic technology, corp. table 1-2. device bus operations ? flash byte mode ( byte_f = v il ) operation (notes 1, 2) ce_f e1_s c ce2_s oe we a0-a19 lb_s (note3) ub_s (note3) reset wp /acc (note 4) i/o 7 ? i/o 0 i/o 15 ? i/o 8 h x read from flash l x l l h a in x x h l/h i out high-z h x write to flash l x l h l a in x x h (note 3) i in i/o 14?8 =hi-z; i/o 15 =a-1 h x standby vcc 0.3 v x l x x x x x vcc_f 0.3 v h high-z high-z h h x l x output disable l l h h x x x l h l/h high-z high-z h x flash hardware reset x x l x x x x x l l/h high-z high-z h x sector protect (notes) l x l h l sa, a6 = l, a1 = h, a0 = l x x v id l/h i in x h x sector unprotect (note 5) l x l h l sa, a6 = h, a1 = h, a0 = l x x v id (note 6) i in x h x temporary sector unprotect x x l x x a in x x v id (note 6) i in high-z h l i out i out h l high-z i out read from sram h l h l h a in l h h x i out high-z h l i in i in l h high-z i in write to sram h l h x l a in l h h x i in high-z legend: l = logic low = v il , h = logic high = v ih , v id = 8.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sector address, a in = address in (for flash byte mode, i/o 15 =a-1), i in = data in, i out = data out notes: 1.other operations except for those indi cated in this column are inhibited. 2.do not apply ce_f = v il , ce1_s = v il and ce2_s = v ih at the same time. 3.don?t care or open lb_s or ub_s . 4.the sector protect and sect or unprotect functions may also be implem ented via programming equipment. see the ?sector/sector block protecti on and unprotection? section. 5. if wp /acc = v il , the two outermost boot sect ors remain protected. if wp /acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotect ed using the method described in ?sector/sector block protection and unprotection?. if wp /acc = v hh , all sectors will be unprotected.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 10 amic technology, corp. word/byte configuration the byte_f pin determines whether the i/o pins i/o 15 -i/o 0 operate in the byte or wo rd configuration. if the byte_f pin is set at logic ?1?, the device is in word configuration, i/o 15 - i/o 0 are active and controlled by ce_f and oe . if the byte_f pin is set at logic ?0?, the device is in byte configuration, and only i/o 0 -i/o 7 are active and controlled by ce_f and oe . i/o 8 -i/o 14 are tri-stated, and i/o 15 pin is used as an input for the lsb(a-1) address function. requirements for reading array data to read array data from the out puts, the system must drive the ce_f and oe pins to v il . ce_f is the power control and selects the device. oe is the output control and gates array data to the output pins. we should remain at v ih . the byte_f pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the devi ce data outputs. each bank remains enabled for read access until the command register contents are altered. see "requirements for reading array data" for more information. refer to the ac read-only operations table for timing specifications and to figure 11 for the timing waveform, l cc1_f in the dc characterist ics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we and ce_f to v il , and oe to v ih . for program operations, the byte_f pin determines whether the device accepts program data in bytes or words, refer to ?word/byte configurat ion? for more information. the device features an unlock bypass mode to facilitate faster programming. once a bank enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. the ?word / byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequence. an erase operation can erase one se ctor, multiple sectors, or the entire device. the sector a ddress tables 3-4 indicate the address range that each sect or occupies. the device address space is divided into two banks: bank 1 contains the boot/parameter sectors, and bank 2 contains the larger, code sectors of uniform size. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. i cc2_f in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contai ns timing specification tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp /acc pin. this function is primarily intended to allow faster manufacturing thro ughput at the factory. if the system asserts v hh on this pin, the device automatically enters the aforementioned unlo ck bypass mode, temporarily unprotects any protected sect ors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp /acc pin returns the device to normal operati on. note that the wp /acc pin must not be at v hh for operations other than accelerated program- ming, or device damage may result. in addition, the wp /acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. autoselect functions if the system writes the autos elect command sequence, the device enters the autoselect m ode. the system can then read autoselect codes from the in ternal register (which is separate from the memory array) on i/o 7 -i/o 0 . standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. simultaneous read/write operations with zero latency this device is capable of r eading data from one bank of memory while programming or er asing in the other bank of memory. an erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). figure 18 shows how read and write cycles may be initiat ed for simultaneous operation with zero latency. i cc6_f and i cc7_f in the dc characteristics table represent the current spec ifications for read-while-pro- gram and read-while-erase, respectively. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are placed in the high impedanc e state, indepen dent of the oe input. the device enters the cm os standby mode when the ce_f & reset pins are both held at vcc_f 0.3v. (note that this is a more restricted voltage range than v ih .) if ce_f and reset are held at v ih , but not within vcc_f 0.3v, the device will be in t he standby mode, but the standby current will be greater. the device requires the standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active curr ent until the operation is completed. i cc3_f in the dc characteristics tables repres ent the standby current specification.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 11 amic technology, corp. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc +30ns. the automatic sleep mode is independent of the ce_f , we and oe control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4_f in the dc characteristics table represents the automatic sleep mode cu rrent specification. reset : hardware reset pin the reset pin provides a hardware method of resetting the device to reading array data. when the system drives the reset pin low for at least a period of t rp , the device immediately terminates any operat ion in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced fo r the duration of the reset pulse. when reset is held at vss 0.3v, the device draws cmos standby current (i cc4_f ). if reset is held at v il but not within vss 0.3v, the standby cu rrent will be greater. the reset pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset is asserted during a progr am or erase operation, the ry/ by pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time t ready (during embedded algorithms). the sy stem can thus monitor ry/ by to determine whether the reset operation is complete. if reset is asserted when a program or erase operation is not executing (ry/ by pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset pin return to v ih . refer to the ac characteristics tables for reset parameters and diagram. output disable mode when the oe input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. table 2. A82DL16X4T(u) device bank divisions bank 1 bank 2 device part number megabits sector sizes megabits sector sizes a82dl1624 2 mbit eight 8 kbyte/4 kword, three 64 kbyte/32 kword 14 mbit twenty-eight 64 kbyte/32 kword a82dl1634 4 mbit eight 8 kbyte/4 kword, seven 64 kbyte/32 kword 12 mbit twenty-four 64 kbyte/32 kword a82dl1644 8 mbit eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword 8 mbit sixteen 64 kbyte/32 kword
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 12 amic technology, corp. table 3. sector addresses for top boot sector devices a82dl1644t a82dl1634t a82dl1624t sector sector address a19?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 00000xxx 64/32 000000h-00ffffh 00000h?07fffh sa1 00001xxx 64/32 010000h-01ffffh 08000h?0ffffh sa2 00010xxx 64/32 020000h-02ffffh 10000h?17fffh sa3 00011xxx 64/32 030000h-03ffffh 18000h?1ffffh sa4 00100xxx 64/32 040000h-04ffffh 20000h?27fffh sa5 00101xxx 64/32 050000h-05ffffh 28000h?2ffffh sa6 00110xxx 64/32 060000h-06ffffh 30000h?37fffh sa7 00111xxx 64/32 070000h-07ffffh 38000h?3ffffh sa8 01000xxx 64/32 080000h-08ffffh 40000h?47fffh sa9 01001xxx 64/32 090000h-09ffffh 48000h?4ffffh sa10 01010xxx 64/32 0a00 00h-0affffh 50000h?57fffh sa11 01011xxx 64/32 0b 0000h-0bffffh 58000h?5ffffh sa12 01100xxx 64/32 0c0000h-0cffffh 60000h?67fffh sa13 01101xxx 64/32 0d0000h-0dffffh 68000h?6ffffh sa14 01110xxx 64/32 0e00 00h-0effffh 70000h?77fffh bank 2 sa15 01111xxx 64/32 0f0000h-0fffffh 78000h?7ffffh sa16 10000xxx 64/32 100000h-10ffffh 80000h?87fffh sa17 10001xxx 64/32 110000h-11ffffh 88000h?8ffffh sa18 10010xxx 64/32 120000h-12ffffh 90000h?97fffh sa19 10011xxx 64/32 130000h-13ffffh 98000h?9ffffh sa20 10100xxx 64/32 140000 h-14ffffh a0000h?a7fffh sa21 10101xxx 64/32 150 000h-15ffffh a8000h?affffh sa22 10110xxx 64/32 160000 h-16ffffh b0000h?b7fffh bank 2 sa23 10111xxx 64/32 170 000h-17ffffh b8000h?bffffh sa24 11000xxx 64/32 180000h-18ffffh c0000h?c7fffh sa25 11001xxx 64/32 190000h-19ffffh c8000h?cffffh sa26 11010xxx 64/32 1a00 00h-1affffh d0000h?d7fffh bank 2 sa27 11011xxx 64/32 1b 0000h-1bffffh d8000h?dffffh sa28 11100xxx 64/32 1c0000 h-1cffffh e0000h?e7fffh sa29 11101xxx 64/32 1d00 00h-1dffffh e8000h?effffh sa30 11110xxx 64/32 1e00 00h-1effffh f0000h?f7fffh sa31 11111000 8/4 1f0000h-1f1fffh f8000h?f8fffh sa32 11111001 8/4 1f2000h-1f3fffh f9000h?f9fffh sa33 11111010 8/4 1f4000h-1f5fffh fa000h?fafffh sa34 11111011 8/4 1f6000h-1f7fffh fb000h?fbfffh sa35 11111100 8/4 1f8000h-1f9fffh fc000h?fcfffh sa36 11111101 8/4 1fa000h-1fbfffh fd000h?fdfffh sa37 11111110 8/4 1fc00 0h-1fdfffh fe000h?fefffh bank 1 bank 1 bank 1 sa38 11111111 8/4 1fe 000h-1fffffh ff000h?fffffh note: the address range is a19: a-1in byte mode ( byte_f =v il ) or a19:a0 in word mode ( byte_f =v ih ). the bank address bits are a19-a17 for a82dl1624t, a19 and a18 for a82dl1634t, and a19 for a82dl1644t.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 13 amic technology, corp. table 4. sector addresses for bottom boot sector devices a82dl1644u a82dl1634u a82dl1624u sector sector address a19?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 00000000 8/4 000000 h-001fffh 00000h-00fffh sa1 00000001 8/4 002000 h-003fffh 01000h-01fffh sa2 00000010 8/4 004000 h-005fffh 02000h-02fffh sa3 00000011 8/4 006000 h-007fffh 03000h-03fffh sa4 00000100 8/4 008000 h-009fffh 04000h-04fffh sa5 00000101 8/4 00a0 00h-00bfffh 05000h-05fffh sa6 00000110 8/4 00c00 0h-00dfffh 06000h-06fffh sa7 00000111 8/4 00e0 00h-00ffffh 07000h-07fffh sa8 00001xxx 64/32 010 000h-01ffffh 08000h-0ffffh sa9 00010xxx 64/32 020 000h-02ffffh 10000h-17fffh bank 1 sa10 00011xxx 64/32 030 000h-03ffffh 18000h-1ffffh sa11 00100xxx 64/32 040 000h-04ffffh 20000h-27fffh sa12 00101xxx 64/32 050 000h-05ffffh 28000h-2ffffh sa13 00110xxx 64/32 060 000h-06ffffh 30000h-37fffh bank 1 sa14 00111xxx 64/32 070 000h-07ffffh 38000h-3ffffh sa15 01000xxx 64/32 080 000h-08ffffh 40000h-47fffh sa16 01001xxx 64/32 090 000h-09ffffh 48000h-4ffffh sa17 01010xxx 64/32 0a 0000h-0affffh 50000h-57fffh sa18 01011xxx 64/32 0b 0000h-0bffffh 58000h-5ffffh sa19 01100xxx 64/32 0c00 00h-0cffffh 60000h-67fffh sa20 01101xxx 64/32 0d00 00h-0dffffh 68000h-6ffffh sa21 01110xxx 64/32 0e 0000h-0effffh 70000h-77fffh bank 1 sa22 01111xxx 64/32 0f 0000h-0fffffh 78000h-7ffffh sa23 10000xxx 64/32 100 000h-10ffffh 80000h-87fffh sa24 10001xxx 64/32 110 000h-11ffffh 88000h-8ffffh sa25 10010xxx 64/32 120 000h-12ffffh 90000h-97fffh sa26 10011xxx 64/32 130 000h-13ffffh 98000h-9ffffh sa27 10100xxx 64/32 140000h-14ffffh a0000h-a7fffh sa28 10101xxx 64/32 150000h-15ffffh a8000h-affffh sa29 10110xxx 64/32 160000h-16ffffh b0000h-b7fffh sa30 10111xxx 64/32 170000h-17ffffh b8000h-bffffh sa31 11000xxx 64/32 180000h-18ffffh c0000h-c7fffh sa32 11001xxx 64/32 190000h-19ffffh c8000h-cffffh sa33 11010xxx 64/32 1a00 00h-1affffh d0000h-d7fffh sa34 11011xxx 64/32 1b00 00h-1bffffh d8000h-dffffh sa35 11100xxx 64/32 1c0000h-1cffffh e0000h-e7fffh sa36 11101xxx 64/32 1d0000h-1dffffh e8000h-effffh sa37 11110xxx 64/32 1e00 00h-1effffh f0000h-f7fffh bank 2 bank 2 bank 2 sa38 11111xxx 64/32 1f 0000h-1fffffh f8000h-fffffh note: the address range is a19: a-1in byte mode ( byte_f =v il ) or a19:a0 in word mode ( byte_f =v ih ). the bank address bits are a19-a17 for a82dl1624u, a19 and a18 for a82dl1634u, and a19 for a82dl1644u.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 14 amic technology, corp. autoselect mode the autoselect mode provides manufacturer and device identification, and sector prot ection verification, through identifier codes output on i/o 7 - i/o 0 . this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (8.5v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 5. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. (see table 3-4). table 5 shows the remaining address bits that are don't care. when all necessary bits have been set as required, the programming equi pment may then read the corresponding identifier code on i/o 7 - i/o 0 . to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 12. this method does not require v id . refer to the autoselect command sequence section for more information. table 5. A82DL16X4T(u) autoselect codes (high voltage method) i/o 8 to i/o 15 description ce_f oe we a19 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 byte_f = v ih byte_f = v il i/o 7 to i/o 0 manufacturer id : amic l l h ba x v id x l x l l x x 37h device id: a82dl1624 l l h ba x v id x l x l h 22h x 2dh (t), 2eh (u) device id: a82dl1634 l l h ba x v id x l x l h 22h x 28h (t), 2bh (u) device id: a82dl1644 l l h ba x v id x l x l h 22h x 33h (t), 35h (b) continuation id l l h x x v id x l x h h x x 7fh read sector protection verification l l h sa x v id x l x h l x x 01h (protected), 00h (unprotected) l=logic low= v il , h=logic high=v ih , sa=sector address, x=don?t care, ba=bank address note: the autoselect codes may also be accessed in-system via command sequences.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 15 amic technology, corp. sector/sector block protection and unprotection (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sector s that are protected or unprotected at the same time (see tables 6 and 7). table 6. top boot sector/sector block addresses for protection/unprotection sector / sector block a19?a12 sector / sector block size sa0 00000xxx 64 kbytes sa1-sa3 00001xxx, 00010xxx, 00011xxx 192 (3x64) kbytes sa4-sa7 001xxxxx 256 (4x64) kbytes sa8-sa11 010xxxxx 256 (4x64) kbytes sa12-sa15 011xxxxx 256 (4x64) kbytes sa16-sa19 100xxxxx 256 (4x64) kbytes sa20-sa23 101xxxxx 256 (4x64) kbytes sa24-sa27 110xxxxx 256 (4x64) kbytes sa28-sa30 11100xxx, 11101xxx, 11110xxx 192 (3x64) kbytes sa31 11111000 8 kbytes sa32 11111001 8 kbytes sa33 11111010 8 kbytes sa34 11111011 8 kbytes sa35 11111100 8 kbytes sa36 11111101 8 kbytes sa37 11111110 8 kbytes sa38 11111111 8 kbytes table 7. bottom boot sector/sector block addresses for protection/unprotection sector / sector block a19?a12 sector / sector block size sa38 11111xxx 64 kbytes sa37-sa35 11110xxx, 11101xxx, 11100xxx 192 (3x64) kbytes sa34-sa31 110xxxxx 256 (4x64) kbytes sa30-sa27 101xxxxx 256 (4x64) kbytes sa26-sa23 100xxxxx 256 (4x64) kbytes sa22-sa19 011xxxxx 256 (4x64) kbytes sa18-sa15 010xxxxx 256 (4x64) kbytes sa14-sa11 001xxxxx 256 (4x64) kbytes sa10-sa8 00001xxx, 00010xxx, 00011xxx 192 (3x64) kbytes sa7 00000111 8 kbytes sa6 00000110 8 kbytes sa5 00000101 8 kbytes sa4 00000100 8 kbytes sa3 00000011 8 kbytes sa2 00000010 8 kbytes sa1 00000001 8 kbytes sa0 00000000 8 kbytes the hardware sector protec tion feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection and unprotection can be implemented via two methods. the primary method requires v id on the reset pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 23 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sector s must first be protected prior to the first sector unprotect write cycle. the sector unprotect algorith m unprotects all sectors in parallel. all previously protect ed sectors must be individually re-protected. to change data in protected sectors efficiently, the temporary sector unprotect function is available. see ?temporary sector/sector block unprotect?. the alternate method for protec tion and unprotection is by software temporary sector /sector block unprotect command. see figure 2 for command flow. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see the autoselect mode section for details. write protect ( wp / acc) the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase func tions in the two ?outermost? 8 kbyte boot sectors independent ly of whether those sectors were protected or unprotected using the method described in ?sector/sector block protection and unprotection?. the two outermost 8 kbyte boot sectors are the two sectors containing the lowest addres ses in a bottom-boot-configured device, or the two sectors co ntaining the highest addresses in a top-boot-configured device. if the system asserts v ih on the wp /acc pin, the device reverts to whether the two ou termost 8 kbyte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection fo r these two sectors depends on whether they were last protec ted or unprotected using the method described in ?sector/sector block protection and unprotection?. note that the wp /acc pin must not be left floating or unconnected; inconsistent behav ior of the device may result. temporary sector/sector block unprotect (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sector s that are protected or unprotected at the same time (see tables 6 and 7). this feature allows temporar y unprotection of previously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset pin to v id (8.5v-12.5v). during this m ode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset pin, all the previously protected sectors are protected again. figure 1 shows the algorithm, and figure 22 shows the timing diagrams, for this feature.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 16 amic technology, corp. start reset = v id (note 1) perform erase or program operations reset = v ih temporary sector unprotect completed (note 2) notes: 1. all protected sectors unprotected (if wp/acc=v il , outermost boot sectors will remain protected). 2. all previously protected sectors are protected once again. figure 1-1. temporary sector unprotect operation by reset mode figure 1-2. temporary sector unpr otect operation by software mode start 555/aa + 2aa/55 + 555/77 (note 1) perform erase or program operations xxx/f0 (reset command) soft-ware temporary sector unprotect completed (note 2) notes: 1. all protected sectors unprotected (if wp/acc=v il , outermost boot sectors will remain protected). 2. all previously protected sectors are protected once again.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 17 amic technology, corp. start plscnt=1 reset=v id wait 1 us first write cycle=60h? set up sector address sector protect: write 60h to sector address with a6=0, a1=1, a0=0 wait 150 us verify sector protect: write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 data=01h?** protect another sector? remove v id from reset write reset command sector protect complete sector protect algorithm temporary sector unprotect mode increment plscnt plscnt =25? device failed no no no yes reset plscnt=1 yes yes no protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address start plscnt=1 wait 1 us first write cycle=60h? no temporary sector unprotect mode yes no all sectors protected? set up first sector address sector unprotect: write 60h to sector address with a6=1, a1=1, a0=0 wait 15 ms verify sector unprotect : write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=00h?** last sector verified? remove v id from reset write reset command sector unprotect complete yes yes set up next sector address no yes yes sector unprotect algorithm increment plscnt plscnt= 1000? device failed yes no no figure 2-1. high voltage sector/sector bl ock protection and unprotection algorithms note: the term ?sector? in the figure applies to both sector s and sector blocks * no other command is allowed during this process ** read access time is 200ns-300ns reset=v id
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 18 amic technology, corp. start plscnt=1 555/aa + 2aa/55 + 555/77 wait 1 us first write cycle=60h? set up sector address sector protect: write 60h to sector address with a6=0, a1=1, a0=0 wait 150 us verify sector protect: write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 data=01h?** protect another sector? write reset command sector protect complete sector protect algorithm temporary sector unprotect mode increment plscnt plscnt =25? device failed no no no yes reset plscnt=1 yes yes no protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address start plscnt=1 wait 1 us first write cycle=60h? no temporary sector unprotect mode yes no all sectors protected? set up first sector address sector unprotect: write 60h to sector address with a6=1, a1=1, a0=0 wait 15 ms verify sector unprotect : write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=00h?** last sector verified? write reset command sector unprotect complete yes yes set up next sector address no yes yes sector unprotect algorithm increment plscnt plscnt= 1000? device failed yes no no figure 2-2. software sector/sector block protection and unprotection algorithms note: the term ?sector? in the figure applies to both sector s and sector blocks * no other command is allowed during this process ** access time is 200ns-300ns 555/aa + 2aa/55 + 555/77
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 19 amic technology, corp. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provi des data protection against inadvertent writes (refer to table 12 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during vcc_f power-up and power-down transitions, or from system noise. low vcc write inhibit when vcc_f is less than v lko , the device does not accept any write cycles. this pr otects data during vcc_f power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until vcc_f is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when vcc_f is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5ns (typical) on oe , ce_f or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe = v il , ce_f = v ih or we = v ih . to initiate a write cycle, ce_f and we must be a logical zero while oe is a logical one. power-up write inhibit if we = ce_f = v il and oe = v ih during power up, the device does not accept commands on the rising edge of we . the internal state machine is automatically reset to reading array data on power-up. common flash memory interface (cfi) the common flash interface (c fi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 8-11. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect m ode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 8-11. the system must write the reset command to return the dev ice to the autoselect mode. table 8. cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists)
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 20 amic technology, corp. table 9. system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h vcc min. (write/erase) i/o 7 - i/o 4 : volt, i /o 3 - i/o 0 : 100 millivolt 1ch 38h 0036h vcc max. (write/erase) i/o 7 - i/o 4 : volt, i /o 3 - i/o 0 : 100 millivolt 1dh 3ah 0000h vpp min. voltage (00h = no vpp pin present) 1eh 3ch 0000h vpp max. voltage (00h = no vpp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) table 10 device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification) 31h 32h 33h 34h 62h 64h 66h 68h 001eh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 40h 0000h 0000h 0000h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 21 amic technology, corp. table 11. primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0032h minor version number, ascii 45h 8ah 0000h address sensitive unlock 0 = required, 1 = not required 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 04 = a29l800 mode 4ah 94h 00xxh (see note) simultaneous operation 00 = not supported, x = number of sectors (excluding bank 1) 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 000xh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device note: the number of sectors in bank 2 is device dependent. a82dl1624 = 1ch a82dl1634 = 18h a82dl1644 = 10h
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 22 amic technology, corp. command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 12 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we or ce_f , whichever happens later. all data is latched on the rising edge of we or ce_f , whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase- suspended sector within the same bank. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if i/o 5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read parameters, and figure 11 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the system was writing to reading array data. once er asure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to reading array data. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if i/o 5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequenc e allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table 12 shows the address and data requirement s. this method is an alternative to that shown in table 5, which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address wit h in a bank that is either in t he read or erase- suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the autoselect command. t he bank then enter s the autoselec t mode. the system may read at any address within the same bank any number of times without initiating another autoselect command sequence: a read cycle at address (ba)xx00h (where ba is the bank address) returns the manufacturer code. a read cycle at address (ba)xx01h in word mode (or (ba)xx02h in byte mode) returns the device code. a read cycle to an address containing a sector address (sa) within the same bank, and the address 02h on a7-a0 in word mode (or the address 04h on a6-a-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (refer to tabl es 3-4 for valid sector addresses). the system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in erase suspend). byte/word program command sequence the system may program the device by word or byte, depending on the state of the byte_f pin. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 12 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, that bank then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using i/o 7 , i/o 6 , or ry/ by . refer to the write operatio n status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the progr am operation. the program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set i/o 5 = 1, or cause the i/o 7 and i/o 6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only eras e operations can convert a ?0? to a ?1.?
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 23 amic technology, corp. start write program command sequence data poll from system verify data ? last address ? programming completed no yes yes increment address embedded program algorithm in progress note : see table 14 for program command sequnce. figure 3. program operation no unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 12 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, t he system must issue the two- cycle unlock bypass reset command sequence. the device then returns to reading array data. the device offers accelerated program operations through the wp /acc pin. when the system asserts v hh on the wp /acc pin, the device automat ically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp /acc pin to accelerate the operation. no te that the wp /acc pin must not be at v hh any operation other than acce lerated programming, or device damage may result. in addition, the wp /acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 3 illustrates the algorith m for the program operation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 15 for timing diagrams.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 24 amic technology, corp. chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 12 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to reading array data and addresses are no longer latched. the system can dete rmine the status of the erase operation by using i/o 7 , i/o 6 , i/o 2 , or ry/ by . refer to the write operation status sect ion for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be rein itiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for par ameters, and figure 17 section for timing diagrams. sector erase command sequence sector erase is a six bus cycl e operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 12 shows the address and data requirements for the sector erase command sequence. the device does not require t he system to preprogram prior to erase. the embedded eras e algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timi ngs during these operations. after the command sequence is wr itten, a sector erase time- out of 50 s occurs. during t he time-out period, additional sector addresses and sector erase commands within the bank may be written. loading the sector erase buffer may be done in any sequence, and t he number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any co mmand other than sector erase or erase suspend during the time- out period resets that bank to reading array data. the syst em must rewrite the command sequence and any additional addresses and commands. the system can monitor i/o 3 to determine if the sector erase timer has timed out (see the section on i/o 3 : sector erase timer.). the time-out begins fr om the rising edge of the final we pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while t he embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading i/o 7 , i/o 6 , i/o 2 , or ry/ by in the erasing bank. refer to the write operation st atus section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be rein itiated once that bank has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for par ameters, and figure 17 section for timing diagrams erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operat ion and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the devi ce requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written dur ing the sector erase time- out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation ha s been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status information on i/o 7 ?i/o 0 . the system can use i/o 7 , or i/o 6 and i/o 2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status sect ion for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the i/o 7 or i/o 6 status bits, just as in the standard byte program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase oper ation, the system must write the erase resume command. the bank address of the erase-suspended bank is ignored when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 25 amic technology, corp. start write erase command sequence (notes 1,2) data poll to erasing bank from system data = ffh ? erasure completed yes embedded erase algorithm in progress note : 1. see table 14 for erase command sequence. 2. see the section on i/o 3 for information on the sector erase timer. no figure 4. erase operation
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 26 amic technology, corp. command definitions table 12. A82DL16X4T(u) command definitions bus cycles (notes 2?5) first second third fourth fifth sixth command sequence (note 1) cycle addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 word 555 2aa (ba)555 manufacturer id byte 4 aaa aa 555 55 (ba)aaa 90 (ba)x00 37 word 555 2aa (ba)555 (ba)x01 device id byte 4 aaa aa 555 55 (ba)aaa 90 (ba)x02 (see table5) word 555 2aa 555 x03 continuation id byte 4 aaa aa 555 55 aaa 90 x06 7f word 555 2aa (ba)555 (sa) autoselect ( note 8 ) sector protect verify (note 9) byte 4 aaa aa 555 55 (ba)aaa 90 (sa)x04 00/01 word 555 2aa 555 command temporary sector unprotect(note 15) byte 3 aaa aa 555 55 aaa 77 word 555 2aa 555 program byte 4 aaa aa 555 55 aaa a0 pa pd word 555 2aa 555 unlock bypass byte 3 aaa aa 555 55 aaa 20 unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 xxx 90 xxx 00 word 555 2aa 555 555 2aa 555 chip erase byte 6 aaa aa 555 55 aaa 80 aa a aa 555 55 aaa 10 word 555 2aa 55 555 80 555 2aa sector erase byte 6 aaa aa 555 aaa aaa aa 555 55 sa 30 erase suspend (note 12) 1 xxx b0 erase resume (note 13) 1 xxx 30 word 55 cfi query (note 14) byte 1 aa 98 legend: x = don't care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be progr ammed. addresses latch on the falling edge of the we or ce_f pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we or ce_f pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode ) or erased. address bits a19 - a12 select a unique sector. ba = address of the bank that is being switched to autos elect mode, is in bypass mode, or is being erased. note: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the four th cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits i/o 15 -i/o 8 are don?t care in command sequences. except for rd and pd. 5. unless otherwise noted, address bits a19-a11 are don?t cares. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if i/o 5 goes high (while the bank is providing status information). 8. the fourth cycle of the autoselect co mmand sequence is a read cycle. the system must provide the bank address to obtain the manufacture id, or device id information. data bits i/o 15 -i/o 8 are don?t care. see the autoselect command sequence section for more information. 9. the data is 00h for an unprotect ed sector/sector block and 01h for a protected sector/sector block. 10. the unlock bypass command is required prior to the unlock bypass program command. 11. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 12. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and require the bank address. 13. the erase resume command is valid only during the erase. 14. command is valid when device is ready to read array data or when device is in autoselect mode. 15. once reset command is applied, software temporary unprotect is exit to return read array data. but under erase suspend condition, this command is still effective even a reset comm and has been applied. the reset command which can deactivate the software temporary unprotect command is usef ul only after the erase command is complete.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 27 amic technology, corp. write operation status the device provides several bits to determine the status of a program or erase operation: i/o 2 , i/o 3 , i/o 5 , i/o 6 , and i/o 7 . table 13 and the following subsections describe the function of these bits. i/o 7 and i/o 6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/ by , to determine whether an embedded program or erase oper ation is in progress or has been completed. i/o 7 : data polling the data polling bit, i/o 7 , indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the embedded program al gorithm, the device outputs on i/o 7 the complement of the datum programmed to i/o 7 . this i/o 7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to i/o 7 . the system must provide the program address to read valid status information on i/o 7 . if a program address falls within a protected sector, data polling on i/o 7 is active for approximately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data polling produces a "0" on i/o 7 . when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a "1" on i/o 7 . the system must provide an address within any of the sectors selected for erasure to read valid status information on i/o 7 . after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on i/o 7 is active for approximately 100 s, then the bank returns to reading array data. if not all sele cted sectors are protected, the embedded erase algorith m erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads i/o 7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, i/o 7 may change asynchronously with i/o 0 ? i/o 6 while output enable ( oe ) is asserted low. that is, the device may change from providing status information to valid data on i/o 7 . depending on when the system samples the i/o 7 output, it may read the status or valid data. even if the device has completed the program or erase operation and i/o7 has valid data, the data outputs on i/o 0 -i/o 6 may be still invalid. valid data on i/o 0 -i/o 7 will appear on successive read cycles. table 13 shows the outputs for data polling on i/o 7 . figure 5 shows the data polling algorithm. figure 19 in the ac characteristics section shows the data polling timing diagram. start read i/o 7 -i/o 0 address = va i/o 7 = data ? fail no note : 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. i/o 7 should be rechecked even if i/o 5 = "1" because i/o 7 may change simultaneously with i/o 5 . no read i/o 7 - i/o 0 address = va i/o 5 = 1? i/o 7 = data ? yes no pass yes yes figure 5. data polling algorithm
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 28 amic technology, corp. ry/ by : ready/ busy the ry/ by is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/ by status is valid after the rising edge of the final we pulse in the command sequence. since ry/ by is an open-drain output, several ry/ by pins can be tied together in parallel with a pull-up resistor to vcc_f. if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (inc luding during the erase suspend mode), or is in the standby mode. table 13 shows the outputs for ry/ by . i/o 6 : toggle bit i toggle bit i on i/o 6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we pulse in the command sequence (prior to the program or erase operation) , and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause i/o 6 to toggle. the system may use either oe or ce_f to control the read cycles. when the operation is complete, i/o 6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, i/o 6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are pr otected, the embedded erase algorithm erases the unprotec ted sectors, and ignores the selected sectors that are protected. the system can use i/o 6 and i/o 2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), i/o 6 toggles. when the device enters the erase suspend mode, i/o 6 stops toggling. however, the system must also use i/o 2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use i/o 7 (see the subsection on " i/o 7 : data polling"). if a program address falls within a protected sector, i/o 6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. i/o 6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 13 shows the outputs for toggle bit i on i/o 6 . figure 6 shows the toggle bit algorithm. figure 20 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 23 shows the differences between i/o 2 and i/o 6 in graphical form. see also the subsection on i/o 2 : toggle bit ii. start read i/o 7 -i/o 0 toggle bit = toggle ? program/erase operation not commplete, write reset command yes note: the system should recheck the toggle bit even if i/o 5 = ? 1 " because the toggle bit may stop toggling as i/o 5 changes to ? 1 ?. see the subsections on i/o 6 and i/o 2 for more information. no read i/o 7 - i/o 0 twice i/o 5 = 1? toggle bit = toggle ? yes yes program/erase operation complete no no read i/o 7 -i/o 0 (notes 1,2) figure 6. toggle bit algorithm (note 1)
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 29 amic technology, corp. i/o 2 : toggle bit ii the "toggle bit ii" on i/o 2 , when used with i/o 6 , indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we pulse in the command sequence. i/o 2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce_f to control the read cycles.) but i/o 2 cannot distinguish whether the sect or is actively erasing or is erase-suspended. i/o 6 , by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required fo r sector and mode information. refer to table 8 to compare outputs for i/o 2 and i/o 6 . figure 6 shows the toggle bit algor ithm in flowchart form, and the section " i/o 2 : toggle bit ii" explains the algorithm. see also the " i/o 6 : toggle bit i" subsection. figure 20 shows the toggle bit timing diagram. figure 21 shows the differences between i/o 2 and i/o 6 in graphical form. reading toggle bits i/o 6 , i/o 2 refer to figure 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read i/o 7 -i/o 0 at least twice in a row to determine whether a toggle bit is toggling. typically, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compar e the new value of the toggle bit with the first. if the toggle bi t is not toggling, the device has completed the program or eras e operation. the system can read array data on i/o 7 -i/o 0 on the following read cycle. however, if after the initia l two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of i/o 5 is high (see the section on i/o 5 ). if it is, the system should then determine again whether the toggle bit is togg ling, since the toggle bit may have stopped toggling just as i/o 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and i/o 5 has not gone high. the system may continue to monitor the toggle bit and i/o 5 through successive read cycles, determining the status as described in the previous paragr aph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 6). i/o 5 : exceeded timing limits i/o 5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions i/o 5 produces a "1." this is a failure condition that indicates the program or erase cycle was not successfully completed. the device may output a ?1? on i/o 5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, i/o 5 produces a ?1.? . under both these conditions, the system must write the reset command to return to reading array data (or to the erase- suspend-read mode if a bank was previously in the erase- suspend-program mode). i/o 3 : sector erase timer after writing a sector erase command sequence, the system may read i/o 3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entir e time-out also applies after each additional sector erase co mmand. when the time-out is complete, i/o 3 switches from "0" to "1." the system may ignore i/o 3 if the system can guar antee that the time between additional sector erase commands will always be less than 50 s. see also the "sector erase command sequence" section. after the sector erase command sequence is written, the system should read the status on i/o 7 ( data polling) or i/o 6 (toggle bit 1) to ensure the device has accepted the command sequence, and then read i/o 3 . if i/o 3 is "1", the internally controlled erase cycle has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if i/o 3 is "0", the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of i/o 3 prior to and following each subsequent sector erase command. if i/o 3 is high on the second status check, the la st command might not have been accepted. table 13 shows the status of i/o 3 relative to the other status bits.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 30 amic technology, corp. table 13. write operation status i/o 7 i/o 6 i/o 5 i/o 3 i/o 2 ry/ by status (note 2) (note 1) (note 2) embedded program algorithm 7 i/o toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspended sector 1 no toggle 0 n/a toggle 1 erase-suspend- read non-erase suspend sector data data data data data 1 erase suspend mode erase-suspend-program 7 i/o toggle 0 n/a n/a 0 notes: 1. i/o 5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on i/o 5 for more information. 2. i/o 7 and i/o 2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bi ts, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 31 amic technology, corp. absolute maximum ratings* storage temperature plastic packages. . . -55 c to +125 c ambient temperature, ????????...-65 c to + 125 c voltage with respect to ground (note 1) vcc_f/vcc_s ???. . . . . . . ? . ... . ??. . -0.5v to +4.0v a9, oe & reset (note 2) . . . . . . . . . . . . -0.5v to +12.5v wp /acc . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +10.5v all other pins (note 1) . . . . . . -0.5v to vcc_f/vcc_s + 0.5v output short circuit current (note 3) . . . . . . . ?. . 200ma notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may undershoot vss to -2.0v for periods of up to 20ns. maximum dc voltage on input and i/o pins is vcc_f/vcc_f +0.5v. see figure 7. during voltage tran sitions, input or i/o pins may overshoot to vcc_f/vcc_s +2.0v for periods up to 20ns. see figure 8. 2. minimum dc input voltage on a9, oe , reset and wp /acc is -0.5v. during voltage transitions, a9, oe , wp /acc and reset may overshoot vss to -2.0v for periods of up to 20ns. see figure 7. maximum dc input voltage on a9 is +12.5v which may overshoot to 14.0v for periods up to 20ns. maximum dc input voltage on wp /acc is +9.5v which may overshoot to +12.0v for period up to 20ns. 3. no more than one output is shorted to ground at a time. duration of the short circuit should not be greater than one second. *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (u) devices ambient temperature (t a ) . . . . . . . . . . . . . . -40 c to +85 c vcc supply voltages vcc_f/vcc_s for all devices . .. . . . . . . ?...+2.7v to +3.6v operating ranges define t hose limits between which the functionally of the dev ice is guaranteed. figure 7. maximum negative overshoot waveform 20ns 20ns 20ns +0.8v -0.5v -2.0v figure 8. maximum positive overshoot waveform 20ns 20ns 20ns vcc_f/vcc_s +0.5v 2.0v vcc_f//vcc_s +2.0v
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 32 amic technology, corp. dc characteristics cmos compatible parameter symbol parameter description test description min. typ. max. unit i li input load current v in = vss to vcc_f. vcc_f= vcc_f max 1.0 a i lit a9 input load current vcc = vcc max, a9 =12.5v 35 a i lo output leakage current vout = vss to vcc_f. vcc = vcc_f max 1.0 a 5 mhz 10 16 ce_f = v il , oe = v ih byte mode 1 mhz 2 4 5 mhz 10 16 i cc1_f vcc_f active read current (notes 1, 2) ce_f = v il , oe = v ih word mode 1 mhz 2 4 ma i cc2_f vcc_f active write current (notes 2, 3) ce_f = v il , oe =v ih 20 30 ma i cc3_f vcc_f standby current (note 2) ce_f = v ih , reset = vcc_f 0.3v 0.2 5 a i cc4_f vcc_f reset current (note 2) reset = vss 0.3v 0.2 5 a i cc5_f automatic sleep mode (note 2, 4) v ih = vcc_f 0.3v ; v il = vss 0.3v 0.2 5 a byte 21 45 i cc6_f vcc_f active read-while-program current (notes 1, 2) ce_f = v il , oe = v ih word 21 45 ma byte 21 45 i cc7_f vcc_f active read-while-erase current (notes 1, 2) ce_f = v il , oe = v ih word 21 45 ma i cc8_f vcc_f active program-while-erase-suspended current (notes 2, 5) ce_f = v il , oe = v ih 17 35 ma acc pin 5 10 i acc acc accelerated program current, word or byte ce_f = v il , oe = v ih vcc_f pin 15 30 ma v il input low level -0.5 0.8 v v ih input high level 0.7 x vcc_f vcc_f + 0.3 v v hh voltage for wp /acc sector protect/unprotect and program acceleration vcc_f = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary unprotect sector vcc_f = 3.0 v 10% 8.5 12.5 v v ol output low voltage i ol = 4.0ma, vcc_f = vcc_f min 0.45 v v oh1 i oh = -2.0 ma, vcc_f = vcc_f min 0.85x vcc_f v v oh2 output high voltage i oh = -100 a, vcc_f = vcc min vcc_f - 0.4 v v lko low vcc_f lock-out voltage (note 5) 2.3 2.5 v notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe at v ih . 2. maximum i cc specifications are tested with vcc_f = vcc_f max. 3. i cc active while embedded algorithm (program or erase) is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc_f + 30ns. typical sleep mode current is 200na. 5. not 100% tested.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 33 amic technology, corp. test conditions table 14. test specifications test condition -70 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 35 pf input rise and fall times 5 ns input pulse levels 0.0 - 3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v figure 9. test setup figure 10. input waveforms and measurement levels measurement level input 1.5v 1.5v output 3.0v 0.0v 6.2 k ? device under test c l diodes = in3064 or equivalent 2.7 k ? 3.3 v
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 34 amic technology, corp. ac characteristics read only operations parameter speed jedec std description test setup -70 unit t avav t rc read cycle time (note 1) min. 70 ns t avqv t acc address to output delay ce_f = v il oe = v il max. 70 ns t elqv t ce chip enable to output delay oe = v il max. 70 ns t glqv t oe output enable to output delay max. 40 ns t ehqz t df chip enable to output high z (notes 1,3) max. 16 ns t ghqz t df output enable to output high z (notes 1,3) max. 16 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min. 0 ns read min. 0 ns t oeh output enable hold time (note 1) toggle and data polling min. 10 ns notes: 1. not 100% tested. 2. see figure 9 and table 14 for test specifications. 3. measurements performed by placing a 50-ohm termination on the data pin with a bias of (vcc_f)/2. the time from oe high to the data bus driven to (vcc_f)/2 is taken as t df . figure 11. read operation timings addresses addresses stable ce_f oe we output valid high-z output t rc t oeh t oe t ce high-z t oh t df t acc 0v reset ry/by t rh t rh
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 35 amic technology, corp. ac characteristics hardware reset ( reset ) parameter jedec std description test setup all speed options unit t ready reset pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rb ry/ by recovery time min 0 ns t rpd reset low to standby mode min 20 s note: not 100% tested. figure 12. reset timings ce_f, oe reset t rh t rp t ready reset timings not during embedded algorithms reset t rp ~ ~ reset timings during embedded algorithms ry/by ~ ~ t rb ~ ~ t ready ce_f, oe ry/by 0v
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 36 amic technology, corp. data output (i/o 0 -i/o 14 ) data output (i/o 0 -i/o 7 ) i/o 15 output address input data output (i/o 0 -i/o 14 ) data output (i/o 0 -i/o 7 ) i/o 15 output address input t fhqv t flqz t elfh t elfl ce_f oe byte_f i/o 0 -i/o 14 i/o 15 (a-1) byte_f i/o 0 -i/o 14 i/o 15 (a-1) byte_f switching from word to byte mode byte _f switching from byte to word mode ac characteristics word/byte configuration ( byte_f ) parameter speed option jedec std description -70 unit t elfl/ t elfh ce_f to byte_f switching low or high max 5 ns t flqz byte_f switching low to output high-z max 25 ns t hqv byte_f switching high to output active min 70 ns figure 13. byte_f timings for read operations figure 14. byte_f timings for write operations note: refer to the erase/program operations table for t as and t ah specifications. the falling edge of the last we signal t hold (t ah ) t set (t as ) ce_f byte_f we
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 37 amic technology, corp. ac characteristics erase and program operations parameter description speed unit jedec std -70 t avav t wc write cycle time (note 1) min. 70 ns t avwl t as address setup time min. 0 ns t aso address setup time to oe low during toggle bit polling 15 ns t wlax t ah address hold time min. 45 ns t aht address hold time from ce_f or oe high during toggle bit polling 0 ns t dvwh t ds data setup time min. 35 ns t whdx t dh data hold time min. 0 ns t oeph output enable high during toggle bit polling min. 20 ns t ghwl t ghwl read recover time before write ( oe high to we low) min. 0 ns t elwl t cs ce_f setup time min. 0 ns t wheh t ch ce_f hold time min. 0 ns t wlwh t wp write pulse width min. 30 ns t whdl t wph write pulse width high min. 30 ns t sr/w latency between read and writ e operations min. 0 byte typ. 5 t whwh1 t whwh1 byte programming operation (note 2) word typ. 7 s t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ. 4 sec t whwh2 t whwh2 sector erase operation (note 2) typ. 0.7 sec t vcs vcc_f set up time (note 1) min. 50 s t rb recovery time from ry/ by min 0 ns t busy program/erase valid to ry/ by delay min 90 ns notes: 1. not 100% tested. 2. see the "erase and programming perfo rmance" section for more information.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 38 amic technology, corp. ac characteristics figure 15. program operation timings figure 16. accelerated program timing diagram wp/acc t vhh ~ ~ v hh v il or v ih t vhh v il or v ih addresses ce_f oe we data vcc_f a0h pd t wc pa program command sequence (last two cycles) pa d out ~ ~ ~ ~ pa ~ ~ status ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data (last two cycles) 555h t ah t whwh1 t ch t wp t wph t cs t ds t dh note : 1. pa = program address, pd = program data, dout is the true data at the program address. 2. illustration shows device in word mode. ~ ~ t rb t busy ry/by
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 39 amic technology, corp. addresses ce_f oe we data vcc_f 55h 30h t wc sa erase command sequence (last two cycles) va complete ~ ~ ~ ~ va ~ ~ in progress ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data 2aah t ah t whwh2 t ch t wp t wph t cs t ds t dh note : 1. sa = sector address (for sector erase), va = valid addr ess for reading status data (see "write operaion ststus"). 2. illustration shows device in word mode. 555h for chip erase 10h for chip erase ~ ~ t rb t busy ry/by ac characteristics figure 17. chip/sector erase operation timings
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 40 amic technology, corp. ac characteristics figure 18. back-to-back read/write cycle timings addresses ce_f oe we data t wc valid ra valid pa valid pa valid out valid in valid pa t rc t wc t wc t ce t acc t cph t cp t oe t ghwl t oeh t wp t wph valid in t ds t dh t sr/w valid in t df t oh t ah we controlled write cycle read cycle ce controlled write cycles figure 19. data polling timings (during embedded algorithms) addresses ce_f oe we i/o 7 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ complement ~ ~ complement true valid data high-z status data ~ ~ status data true valid data high-z i/o 0 - i/o 6 t acc t ce t ch t oe t oeh t df t oh note : va = valid address. illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. ~ ~ t busy ry/by high-z
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 41 amic technology, corp. ac characteristics figure 20. toggle bit timings (during embedded algorithms) addresses ce_f oe we i/o 6 , i/o 2 ~ ~ ~ ~ valid status t oeh valid status valid status valid data ~ ~ (first read) (second read) (stop togging) ry/by ~ ~ ~ ~ ~ ~ t as t aht t ceph t aht t aso valid status t oeph t oe t dh note: va = valid address; not required for i/o 6 . illustration shows first two status cy cle after command sequence, last status read cycle, and array data read cycle. figure 21. i/o 2 vs. i/o 6 enter embedded erasing erase suspend enter erase suspend program erase resume we i/o 6 i/o 2 erase erase suspend read erase suspend read erase erase complete i/o 2 and i/o 6 toggle with oe and ce_f note : both i/o 6 and i/o 2 toggle with oe or ce_f. see the text on i/o 6 and i/o 2 in the section "write operation status" for more information. ~ ~ ~ ~ ~ ~ erase suspend program ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 42 amic technology, corp. ac characteristics temporary sector/sector block unprotect parameter jedec std description all speed options unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 s t rsp reset setup time for temporary sector/sector block unprotect min 4 s t rrb reset hold time from ry/ by high for temporary sector/sector block unprotect min 4 s note: not 100% tested. figure 22. temporary sector/sector block unprotect timing diagram program or erase command sequence reset ~ ~ ~ ~ ~ ~ v id v ss , v il , or v ih t vidr t vidr t rsp ce_f we ry/by ~ ~ v id v ss , v il , or v ih t rrb program/erase command sequence 555 2aa 555 xxx ~ ~ ~ ~ aa 55 77 fq ~ ~ ~ ~ ce_f we ry/by address i/o 0 - i/o 7
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 43 amic technology, corp. ac characteristics figure 23. sector/sector block protect and unprotect timing diagram v id note : for sector protect, a6=0, a1=1, a0=0. for sector unprotect, a6=1, a1=1, a0=0 ~ ~ ~ ~ ~ ~ ~ ~ v ih reset sa, a6, a1, a0 data ce we oe valid* valid* valid* 60h 60h 40h status sector protect/unprotect verify 1us sector protect:150us sector unprotect:15ms 200ns-300ns
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 44 amic technology, corp. ac characteristics alternate ce_f controlled erase and program operations parameter speed jedec std description -70 unit t avav t wc write cycle time (note 1) min. 70 ns t avel t as address setup time min. 0 ns t elax t ah address hold time min. 45 ns t dveh t ds data setup time min. 35 ns t ehdx t dh data hold time min. 0 ns t ghel t ghel read recover time before write ( oe high to we low) min. 0 ns t wlel t ws we setup time min. 0 ns t ehwh t wh we hold time min. 0 ns t eleh t cp ce_f pulse width min. 30 ns t ehel t cph ce_f pulse width high min. 30 ns byte typ. 5 t whwh1 t whwh1 programming operation (note 2) word typ. 7 s t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ. 4 s t whwh2 t whwh2 sector erase operation (note 2) typ. 0.7 sec notes: 1. not 100% tested. 2. see the "erase and programming perfo rmance" section for more information.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 45 amic technology, corp. ac characteristics figure 24. alternate ce_f controlled write (erase/program) operation timings addresses we oe ce_f data 555 for program 2aa for erase pa d out ~ ~ ~ ~ i/o 7 ~ ~ ~ ~ ~ ~ data polling pd for program 30 for sector erase 10 for chip erase ~ ~ t busy t whwh1 or 2 t ah t as t wc t wh t cp t ws t cph pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase t rh t ds t dh ~ ~ ~ ~ reset ry/by t ghel notes: 1. figure indicates last two bus cycl es of a program or erase operation. 2. pa = program address, sa = sect or address, pd = program data. 3. 7 i/o is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 46 amic technology, corp. sram dc electrical characteristics (t a = -40 c to +85 c, vcc_s = 2.7v to 3.6v, gnd = 0v) symbol parameter - 70 ns unit conditions min. max. ? i li ? input leakage current - 1 a v in = gnd to vcc_s ? i lo ? output leakage current - 1 a ce1_s = v ih or ce2_s = v il or oe = v ih or we = v il v i/o = gnd to vcc i cc_s active power supply current - 3 ma ce1_s = v il , ce2_s = v ih i i/o = 0ma i cc1_s dynamic operating - 30 ma min. cycle, duty = 100% ce1_s = v il , ce2_s = v ih i i/o = 0ma i cc2_s current - 3 ma ce1_s = v il , ce2_s = v ih v ih = vcc_s, v il = 0v f = 1 mh z, i i/o = 0ma i sb_s - 0.5 ma vcc_s 3.3v , ce1_s = v ih or ce2_s =v il i sb1_s standby power supply current - 5 a vcc 3.3v, ce1_s vcc - 0.2v or ce2_s 0.2v, v in 0v v ol output low voltage - 0.4 v i ol = 2.1ma v oh output high voltage 2.2 - v i oh = -1.0ma truth table mode ce1_s ce2_s oe we i/o operation supply current standby h x x x high z i sb , i sb1 x l x x high z i sb , i sb1 output disable l h h h high z i cc, i cc1, i cc2 read l h l h d out i cc, i cc1, i cc2 write l h x l d in i cc, i cc1, i cc2 note: x = h or l
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 47 amic technology, corp. capacitance (t a = 25 c, f = 1.0mhz) symbol parameter min. max. unit conditions c in * input capacitance 6 pf v in = 0v c i/o * input/output capacitance 8 pf v i/o = 0v * these parameters are sampled and not 100% tested.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 48 amic technology, corp. ac characteristics (t a = -40 c to +85 c, vcc_s = 2.7v to 3.6v) symbol parameter -70 ns unit min. max. read cycle t rc read cycle time 70 - ns t aa address access time - 70 ns t ace1 chip enable access time ce1_s - 70 ns t ace2 ce2_s - 70 ns t oe output enable to output valid - 35 ns t clz1 chip enable to output in low z ce1_s 10 - ns t clz2 ce2_s 10 - ns t olz output enable to output in low z 5 - ns t chz1 chip disable to output in high z ce1_s 0 25 ns t chz2 ce2_s 0 25 ns t ohz output disable to output in high z 0 25 ns t oh output hold from address change 10 - ns write cycle t wc write cycle time 70 - ns t cw chip enable to end of write 60 - ns t as address setup time 0 - ns t aw address valid to end of write 60 - ns t wp write pulse width 50 - ns t wr write recovery time 0 - ns t whz write to output in high z 0 25 ns t dw data to write time overlap 30 - ns t dh data hold from write time 0 - ns t ow output active from end of write 5 - ns notes: t chz1 , t chz2 , t ohz , and t whz are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 49 amic technology, corp. timing waveforms read cycle 1 (1, 2, 4) t rc t oh t aa t oh address dout read cycle 2 (1, 3, 4, 6) tclz1 5 tace1 tchz1 5 ce1_s dout read cycle 3 (1, 4, 7, 8) tclz2 5 tace2 tchz2 5 ce2_s dout
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 50 amic technology, corp. timing waveforms (continued) read cycle 4 (1) t rc address ce2_s dout t aa t oe t olz 5 t ace1 t clz1 5 t ace2 t clz2 5 t chz2 5 t ohz 5 t chz1 5 t oh ce1_s oe notes: 1. we is high for read cycle. 2. device is continuously enabled ce1_s = v il and ce2_s = v ih . 3. address valid prior to or coincident with ce1_s transition low. 4. oe = v il . 5. transition is measured 500mv from steady state. this parameter is sampled and not 100% tested. 6. ce2_s is high. 7. ce1_s is low. 8. address valid prior to or coincident with ce2_s transition high. write cycle 1 (6) (write enable controlled) t wc address ce1_s ce2_s din t o w t dh t d w t whz t wp 2 t as 1 (4) t cw 5 t aw t wr 3 we dout (4)
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 51 amic technology, corp. timing waveforms (continued) write cycle 2 (chip enable controlled) t wc address ce1_s ce2_s din t dh t dw (4) (4) t cw 5 t aw t wr 3 we dout t whz 7 t wp 2 t cw 5 t as 1 notes: 1. t as is measured from the address valid to the beginning of write. 2. a write occurs during the overlap (t wp ) of a low ce1_s , a high ce2_s and a low we . 3. t wr is measured from the earliest of ce1_s or we going high or ce2_s going low to the end of the write cycle. 4. if the ce1_s low transition or the ce2_s high transition occurs simultaneously with the we low transition or after the we transition, outputs remain in a high impedance state. 5. t cw is measured from the later of ce1_s going low or ce2_s going high to the end of write. 6. oe is continuously low. ( oe = v il ) 7. transition is measured 500mv from steady state. this parameter is sampled and not 100% tested.
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 52 amic technology, corp. sram data retention characteristics (t a = -40 c to 85 c) symbol parameter min. max. unit conditions v dr1 2.0 3.6 v ce1_s vcc - 0.2v v dr2 vcc for data retention 2.0 3.6 v ce2_s 0.2v, i ccdr1_s data retention current - 1* a vcc_s = 2v, ce1_s vcc_s - 0.2v, v in 0v i ccdr2_s - 1* a vcc_s = 2v, ce2_s 0.2v, v in 0v t cdr chip disable to data retention time 0 - ns see retention waveform t r operation recovery time 5 - ms * i ccdr_s : max. 1 a at t a = 0 c to + 40 c low vcc data retention waveform (1) ( ce1_s controlled) vcc_s ce1_s t cdr v ih 3.0v t r v ih 3.0v data retention mode vdr _ 2v ce1_s vdr - 0.2v low vcc data retention waveform (2) (ce2_s controlled) vcc_s ce2_s t cdr v il 3.0v t r v il 3.0v data retention mode vdr_s 2.0v ce2_s 0.2v
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 53 amic technology, corp. erase and programming performance parameter typ. (note 1) max. (note 2) unit comments sector erase time 0.7 15 sec chip erase time 27 sec excludes 00h programming prior to erasure (note 4) byte programming time 5 150 s word programming time 7 210 s accelerated word/byte programming time 4 120 s byte mode 9 27 sec chip programming time (note 3) word mode 6 18 sec excludes system-level overhead (note 5) notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0v vcc_f, 10,000 cycles. additionally, programming typically assumes checkerboard pattern. 2. under worst case conditions of 90 c, vcc_f = 2.7v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. 4. in the pre-programming step of the embedded erase al gorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle command sequence for programming. see table 12 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 10,000 cycles. flash latch-up characteristics description min. max. input voltage with respect to vss on all i/o pins -1.0v vcc+1.0v vcc_f current -100 ma +100 ma input voltage with respect to vss on all pins except i/o pins (including a9, oe and reset ) -1.0v 12.5v includes all pins except vcc_f. test conditions: vcc_f = 3.0v, one pin at time. data retention parameter test conditions min unit 150 c 10 years minimum pattern data retention time 125 c 20 years
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 54 amic technology, corp. ordering information top boot sector flash & sram part no. access time (ns) bank 1 bank 2 package a82dl1624tg-70 69-ball tfbga a82dl1624tg-70f 69-ball pb-free tfbga a82dl1624tg-70i 69-ball tfbga a82dl1624tg-70if 69-ball pb-free tfbga a82dl1624tg-70u 69-ball tfbga a82dl1624tg-70uf 70 2m 14m 69-ball pb-free tfbga a82dl1634tg-70 69-ball tfbga a82dl1634tg-70f 69-ball pb-free tfbga a82dl1634tg-70i 69-ball tfbga a82dl1634tg-70if 69-ball pb-free tfbga a82dl1634tg-70u 69-ball tfbga a82dl1634tg-70uf 70 4m 12m 69-ball pb-free tfbga a82dl1644tg-70 69-ball tfbga a82dl1644tg-70f 69-ball pb-free tfbga a82dl1644tg-70i 69-ball tfbga a82dl1644tg-70if 69-ball pb-free tfbga a82dl1644tg-70u 69-ball tfbga a82dl1644tg-70uf 70 8m 8m 69-ball pb-free tfbga note: industrial operating temperature range: -40 c to 85 c for ?u; -25 c to 85 c for ?i
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 55 amic technology, corp. bottom boot sector flash & sram part no. access time (ns) bank 1 bank 2 package a82dl1624ug-70 69-ball tfbga a82dl1624ug-70f 69-ball pb-free tfbga a82dl1624ug-70i 69-ball tfbga a82dl1624ug-70if 69-ball pb-free tfbga a82dl1624ug-70u 69-ball tfbga a82dl1624ug-70uf 70 2m 14m 69-ball pb-free tfbga a82dl1634ug-70 69-ball tfbga a82dl1634ug-70f 69-ball pb-free tfbga a82dl1634ug-70i 69-ball tfbga a82dl1634ug-70if 69-ball pb-free tfbga a82dl1634ug-70u 69-ball tfbga a82dl1634ug-70uf 70 4m 12m 69-ball pb-free tfbga a82dl1644ug-70 69-ball tfbga a82dl1644ug-70f 69-ball pb-free tfbga a82dl1644ug-70i 69-ball tfbga a82dl1644ug-70if 69-ball pb-free tfbga a82dl1644ug-70u 69-ball tfbga a82dl1644ug-70uf 70 8m 8m 69-ball pb-free tfbga note: industrial operating temperature range: -40 c to 85 c for ?u; -25 c to 85 c for ?i
A82DL16X4T(u) series preliminary (august, 2005, version 0.0) 56 amic technology, corp. package information 69ld stf bga (8 x 11mm) outline dimensions unit: mm 8 7 6 5 4 3 2 1 a b c d e f g h j k -a- -b- pin #1 d e aaa aaa see detail a 910 d 1 e e 1 -c- ccc c cavity seating plane solder ball c a 1 a 2 a 123 a b c see detail b b detail a detail b c ddd c m eee m a b // bbb c dimensions in mm dimensions in inches symbol min nom max min nom max a - - 1.40 - - 0.055 a 1 0.25 0.30 0.35 0.010 0.012 0.014 a 2 0.91 0.96 1.01 0.036 0.038 0.040 c 0.22 0.26 0.30 0.009 0.010 0.012 d 7.90 8.00 8.10 0.311 0.315 0.319 e 10.90 11.00 11.10 0.429 0.433 0.437 d1 - 7.20 - - 0.283 - e1 - 7.20 - - 0.283 - e - 0.80 - - 0.031 - b 0.35 0.40 0.45 0.14 0.16 0.18 aaa 0.15 0.006 bbb 0.20 0.008 ccc 0.12 0.005 ddd 0.15 0.006 eee 0.08 0.003 md/me 10/10 10/10 notes: 1. primary datum c and seating plane are defined by the spherical crowns of the solder balls. 2. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. 3. there shall be a minimum clearance of 0.25mm between the edge of the solder ball and the body edge. 4. reference document : jedec mo-219 5. the pattern of pin 1 fiducial is for reference only.

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